R. Colin Johnson (12/04/2007 10:09 AM EST)
PORTLAND, Ore. — A high-k dielectric process for CMOS transistors promises to turn the International Semiconductor Roadmap into a freeway by eliminating the gate-leakage problem at advanced nodes down to 10 nanometers.
Overheating due to excessive gate leakage is the number one hurdle to reaching advanced semiconductor nodes below 45 nanometer. Now, a process with 1 million times less gate leakage could enable rapid migration to advanced nodes, according to Clemson University researchers.
The rapid-thermal process of atomic layer deposition achieved an effective gate oxide thickness (EOT) of 0.39 nanometers with only 10-12A/cm2.
"This is a process that is robust and manufacturing tools could be developed for it without any fundamental barriers. We are using standard CVD techniques and the same precursors as everybody else," said Rajendra Singh, director of the Center for Silicon Nanoelectronics at Clemson University. "The difference comes from our optimized process chemistry and our use of different kinds energy sources—that's what our patent covers."
As gate oxide thickness were slimmed for 45-nm nodes and below, the industry has moved to using high-k dielectrics. For instance, Clemson's hafnium gate oxide high-k dilectric measured 2.4 nanometers in thickness, but had an EOT of 0.39 nanometers when compared to conventional silicon dioxide.
The semiconductor roadmap calls for high-k dielectrics at the 65-nm node, but most manufacturers, including Intel Corp., have delayed going to high-K dielectrics until the 45-nm node. The reason is that manufacturers would have to solve the problem of higher gate leakages through dielectrics that insulate less well than silicon dioxide.
Clemson's results indicate that such high-k dielectrics were the right way to go, and should take the industry down to the 10-nm node.
"It has signiýcant impact on silicon IC manufacturing industry," said Singh. "Semiconductor manufacturers are currently debating whether its worth the cost to change to larger 450-millimeter wafers, but using our invention eliminates several processing steps resulting in an overall reduction in costs at advanced nodes."
